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4 .0 FUNCTIONAL DESCRIPTION
Input data from the host system is loaded into the module’s display buffer via the
serial data input channel. The internal timing and control system synchronizes the
signal and digit output signals to provide correct timing for the multiplexing
operation. A 16 x 64 bit programmable logic array (PLA) is provided for segment
decoding of the full upper-case ASCII character set. Input data from the host
system is loaded as a series of 8-bit data bytes clocked in on the high to low
transition of the clock.
Control and Character Data Bytes
The most significant bit (bit 7) is loaded first and is referred to as the control bit
(C-bit). If the C-bit of any byte is logical 1, the byte is a control data byte; if it is
logical 0, the byte is a character data byte. The functions and formats of control and
character data bytes are described in detail below.
4.1 WRITING CONTROL DATA BYTES
When the C-bit of the loaded byte is logical 1, it is recognized as a control data
byte. See table below for the format and explanation of each.
8-BIT CONTROL
BYTE
7 6 5 4 3 2 1 0
FUNCTION
1 0 1 0 X X X X
Load Buffer Pointer
(position of character to be defined)
1 1 0 0 Y Y Y Y
Load Digit Counter
(number of characters to be displayed)
1 1 1 Z Z Z Z Z
Load Duty Cycle
(luminance level control)
Notes: 1. “XXXX” – 4 bit binary value of the digit position to be written to
2. “YYYY” – 4 bit binary value of the number of characters to be displayed
3. “ZZZZZ”– 5 bit binary va
lue divided by 31 times 100% equals
luminance level.
相关PDF资料
M0116SY-161MSAR1 MODULE VF CHAR 1X16 5MM
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M0216SD-162SDAR2-1 MODULE VF CHAR 2X16 5.34MM
M0216SD-162SDAR8 MODULE VF CHAR 2X16 5.34MM
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